Digital timing recovery loop for GMSK demodulators
US6411661B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 1999 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | May 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0046
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A GMSK timing recovery loop in a receiver of a Gaussian Minimum Shift Keying (GMSK) link with a low channel Bit Signal-to-Noise Ratio (BSNR) and a small bandwidth-bit period BT product in a high bandwidth efficiency channel, includes a hard limiter for converting at baseband a GMSK demodulated received signal into a hard clocking signal clocking a conventional digital tracking transition loop generating the bit timing signal in closed loop control for stable time tracking performance for coherent demodulation of GMSK signals. The hard limiter provides the hard clocking signal at baseband having transitions at multiple bit periods adjusted by the bit timing error signal from the digital tracking transition loop for providing reduced jitter of the bit timing signal for accurate timing recovery and detection of communicated data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.