Microprocessor with virtual-to-physical address translation using flags
US6412057B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 1999 |
| Grant date | Jun 25, 2002 |
| Priority date | — |
| Expiry date | Feb 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor includes an MMU which converts from a virtual address to a physical address, and an LSU which controls an execution of a load/store instruction. The LSU includes a DCACHE which temporarily stores data to read out from and to write into an external memory, an SPRAM used for a specific purpose besides caching, and an address generator which generates the virtual address to access the DCACHE and the SPRAM. The MMU generates a conversion table which performs a conversion from the virtual address to the physical address. A flag information showing whether or not the access to the SPRAM is performed is included in this conversion table. The LSU absolutely accesses the SPRAM if the flag is being set. Accordingly, it is unnecessary to allocate the SPRAM to a memory map of the main memory, and the allocation of the memory map simplifies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.