Semiconductor structure and fabrication method of shallow and deep trenches

US6413835B1 · kind B1 · utility

Assignee

• Telefonaktiebolaget LM Ericsson (Publ) · SE

Inventors

• Hans Norstrom · Solna, SE
• Carl Bjormander · Spånga, SE
• Ted Johansson · Djursholm, SE

Key dates

• Filing date: Sep 15, 2000
• Grant date: Jul 2, 2002
• Expiry date: Sep 15, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76232
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In the fabrication of an integrated circuit, particularly an integrated circuit for radio frequency applications, a method for forming shallow and deep trenches for isolation of semiconductor devices comprised in said circuit, comprising providing a semiconductor substrate; optionally forming a first dielectric layer on said substrate; forming at least one shallow trench by using a first mask, said shallow trench extending into said substrate; forming a second dielectric layer of a predetermined thickness on the structure obtained subsequent to the step of forming at least one shallow trench; forming at least one opening in said second dielectric layer by using a second mask with an edge of said second mask aligned to an edge of said shallow trench with a maximum misalignment of half the predetermined thickness, said opening extending within the shallow trench to the bottom thereof, whereby a spacer of a width equal to the predetermined thickness is formed in said shallow trench and along said edge thereof; and forming a deep trench in said opening by using said second dielectric layer as a hard mask, said deep trench extending further into said substrate and being self-aligned to …