Semi-conductor device with test element group for evaluation of interlayer dielectric and process for producing the same
US6414334B2 · kind B2 · utility
1Cited by
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8Claims
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Key dates
| Filing date | May 11, 2001 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | May 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device 10 with Test Element Group (TEG) for estimating an interlayer dielectric includes a memory cell array. The memory cell array includes a semiconductor substrate 1, and a floating gate 2, an interlayer dielectric 3, and a control gate 4, all formed on the substrate 1 in this order. The TEG has the memory cell array similar to semiconductor device subject to estimation for the interlayer dielectric 3. The floating gate 2 has an electrode 5 for estimating the interlayer dielectric 3 provided on at least one side against an elongated direction of the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.