Semiconductor device
US6414393B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2000 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | Dec 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a semiconductor device having a multilayer wiring structure in which a plurality of layers are provided on a substrate and in which a connection wiring is formed on each layer, wherein a dummy pattern almost as high as the connection wiring is provided in a predetermined region of each layer so that an outer peripheral portion of the dummy pattern is adjacent to the connection wiring, the dummy pattern is formed linearly at least on the outer peripheral portion, and a distance between a linearly formed portion and a portion inside of the linearly formed portion is set to be equal to or narrower than a distance between the connection wiring and the linearly formed portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.