Over-voltage tolerant, active pull-up clamp circuit for a CMOS crossbar switch
US6414533B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 23, 1999 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | Nov 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/162
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS bus switch (20) having undershoot protection circuitry (22) to help prevent data corruption when the switch is open and the buses (A,B) are isolated from one another. A bias generator (30) sets a voltage (Bias) referenced to ground which allows the active pull-up clamp to turn on when the bus voltage goes negative. This clamp attempts to counteract the undershoot voltage and limit the Vgd or Vgs of the N-channel pass transistor (MN1) and the Vbe of the parasitic NPN transistor. Since the active pull-up clamp circuit is also over-voltage tolerant, this invention will work equally well in high, low, and mixed voltage systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.