Multiplexing pixel circuits
US6414665B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1998 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | Nov 4, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2300/0814
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An active matrix display in accordance with the present invention includes a plurality of pixels arranged in an array. At least two transistors associated with each pixel are included. The transistors are serially connected to each other and disposed within the array for switching the pixels on and off according to data and gate signals. A data line is coupled to a first end of the serially connected transistors for each pixel. A second end of the serially connected transistors is coupled to a storage device. The serially connected transistors provide multiplexing capability for at least one of data signal multiplexing and gate signal multiplexing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.