Semiconductor memory device having column redundancy scheme to improve redundancy efficiency
US6414896B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2001 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | Jul 13, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having a column redundancy scheme for improving redundancy efficiency includes sub memory blocks, a redundancy memory block, global data input output lines respectively associated with the sub memory blocks, a redundancy global data input output line and switches. Each of the sub memory blocks has a plurality of memory cells. The redundancy memory block has a plurality of redundancy memory cells. The data of selected memory cells of a sub memory block are transmitted to a corresponding global data input output line. The data of selected redundancy memory cells of the redundancy memory block are transmitted to the redundancy global data input output line. A switch switches the global data input output line to the redundancy global data input output line if a memory cell connected to the global data input output line is defective.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.