Reducing waiting time jitter
US6415006B2 · kind B2 · utility
15Cited by
32References
43Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 23, 2001 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | Feb 23, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/073
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Circuits and methods are described which reduce waiting time jitter at a synchronizer/multiplexer by using a “sub-bit” comparison of a clock associated with an unsynchronized data stream and a clock associated with a synchronized data stream to generate a threshold level for use in determining when to stuff bits into the synchronized data stream. The term “sub-bit” means that the phase difference, as measured by, for example, the location of pointers associated with the two clocks, is precise to a fraction of a bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.