Apparatus for controlling cache by using dual-port transaction buffers
US6415361B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2000 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | Jan 19, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for controlling a cache in a computing node, which is located between a node bus and an interconnection network to perform a cache coherence protocol, includes: a node bus interface for interfacing with the node bus; an interconnection network interface for interfacing with the interconnection network; a cache control logic means for controlling the cache to perform the cache coherence protocol; bus-side dual-port transaction buffers coupled between said node bus interface and said cache control logic means for buffering transaction requested and replied from or to local processors contained in the computing node; and network-side dual-port transaction buffers coupled between said interconnection network interface and said cache control logic for buffering transaction requested and replied from or to remote processors contained in another computing node coupled to the interconnection network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.