Apparatus for reducing asynchronous service latency in a time slot-based memory arbitration scheme
US6415367B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1999 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | Dec 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/161
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Access to a memory is arbitrated by a memory arbiter. A plurality of first counters in the memory arbiter decrements service periods associated with isochronous memory requests, and a second counter decrements a service period associated with asynchronous memory requests, with the service periods for the first and second memory requests together comprising a schedule period. A scheduler logic circuit receives isochronous and asynchronous memory requests and generates a grant signal to service a received asynchronous request during the schedule period if time remains in the second counter or if there are no pending isochronous memory requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.