Shared devices and memory using split bus and time slot interface bus arbitration
US6415369B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2000 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | Sep 11, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4031
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus allowing efficient access control to a common data bus by including an isolation device to separate the common data bus, a priority-based arbiter to control access to the internal portion of the common data bus including a processor or other bus master, and a time slot arbiter to control access to the external portion of the common data bus including multiple bus masters, an external memory interface, etc. The common external memory may be allocated for exclusive or non-exclusive use by the various devices utilizing either portion of the isolated common data bus. External devices accessing the external memory may communicate directly with one or more bus masters, e.g., on the internal portion of the common data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.