Synthesizing sequential devices from hardware description languages (HDLS)
US6415420B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 1999 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | Jul 15, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method using at least a portion of a control data flow graph (CDFG) which includes multiple control structures in a computer readable storage medium representing at least a portion of a high level design language (HDL) description of an actual or planned logic circuit to evaluate a need for a sequential state element in the portion of the logic circuit comprising producing a graph structure in the storage medium by providing a path origination node in the storage medium; providing a path destination node in the storage medium; producing respective complete paths between the path origination node and the path destination node by separately concatenating each branch of a first control structure of the CDFG with each branch of a second control structure of the CDFG such that a different respective complete path is produced for each possible combination of a respective branch from the first control structure and a respective branch from the second control structure; associating respective complete paths with a respective control statements associated in the CDFG with corresponding branches that have been concatenated with other corresponding branches to produce such respective comple…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.