Nonvolatile semiconductor memory equipped with data latch circuits for transferring one-bit data or multi-bit data
US6418052B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2001 |
| Grant date | Jul 9, 2002 |
| Priority date | — |
| Expiry date | Oct 12, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data latch circuits are provided corresponding to select memory cells from or into which read or program is executed. The data latch circuits are grouped by two into sets. When 2-bit data is read from or programmed into the select memory cells, one data latch circuit is selected by a select signal, and, when 1-bit data is read or programmed, the two data latch circuits in one set are selected by a select signal. Between one or two selected data latch circuits and a data input/output buffer, data is exchanged. By so doing, changeover between 2-level data and multi-level (4-level or more-level) data concerning program or read of data into or out the memory cells becomes possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.