Forwarded clock recovery with variable latency
US6418176B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 1998 |
| Grant date | Jul 9, 2002 |
| Priority date | — |
| Expiry date | Jul 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A technique provides data from an information signal. The technique involves receiving the information signal in the forwarded clock device synchronously with a forwarded clock signal. The technique further involves recovering data contained within the information signal synchronously with a recovery clock signal such that the data is recovered with (i) a particular cycle latency when the recovery clock signal has an optimal rate for the forwarded clock device, and (ii) a different cycle latency when the recovery clock signal has a sub-optimal rate. The particular cycle latency may include more cycles than the different cycle latency. As such, the time latency may be shorter when the recovery clock signal has the sub-optimal rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.