Circuit designing method for semiconductor device and computer-readable medium
US6418553B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2000 |
| Grant date | Jul 9, 2002 |
| Priority date | — |
| Expiry date | Mar 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There are provided a circuit designing method using a half-tone phase shift mask for forming a circuit pattern on a semiconductor substrate, and a computer-readable medium having recorded a program for causing a computer to execute the circuit designing method. The circuit designing method comprises the steps of: calculating a first lithography process tolerance, which is an index satisfying a range of a dimensional fluctuation allowed when a basic pattern representative of the circuit pattern is formed on the semiconductor substrate, and calculating a second lithography process tolerance, which is an index capable of avoiding the formation of a side lobe capable of being produced on the semiconductor substrate when the basic pattern is formed on the semiconductor substrate using the half-tone phase shift mask, respectively, using an optical simulation; calculating a common lithography process tolerance comprising an overlapping region of the first lithography process tolerance and the second lithography process tolerance; preparing an inhibiting rule for excluding a circuit pattern including the basic pattern, which is below a reference value previously set on the basis of the com…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.