Method and arrangement for dielectric integrity testing using PLL loop capacitor
US6420880B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 23, 1999 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Sep 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/013
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor testing process effectively determines the integrity of a large capacitive structure buried within an integrated circuit. According to one example embodiment, a process of testing the oxide integrity of a circuit involves selecting a large gate oxide structure or structures that can be isolated from leakage paths. The dielectric integrity of the structure is tested by stressing the structure via voltage settings, comparable to a supply voltage, across its two terminals. The structure is connected to a current-sensitive node in-the integrated circuit across the two terminals. Other circuits connected to the current-sensitive node are shut off so that the current-sensitive node should be an island relative to other current paths. The leakage current at the current-sensitive node is then measured and compared with a reference level. From the measurements and comparison, a quality factor indicative of the dielectric integrity in the structure is determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.