High-sensitivity, self-clocked receiver for multi-chip superconductor circuits
US6420895B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2001 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Mar 23, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver (50) for providing chip-to-chip communication in a superconductor integrated circuit. The receiver (50) includes a detector circuit (52) for asynchronously receiving an input current, a splitter circuit (60) connected to the detector circuit (52) for generating first and second signals, a delay circuit (62) receiving the second signal from the splitter circuit for generating a delayed signal and a register circuit (64) receiving the first signal from the splitter circuit (60) and the delayed signal from the delay circuit (62) for producing a single flux quantum (SFQ) pulse. The receiver (50) according to the present invention provides an asynchronous chip-to-chip communication between a multi-chip superconductive circuit having low input current without an external rf clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.