Domino logic with self-timed precharge
US6420904B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2001 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Jan 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The precharge of a domino logic stage is controlled based on the precharge delay of a prior domino logic stage. The precharge of the logic stage does not occur until the output of the prior logic stage corresponds to the precharge logic state. Because the precharge logic state output of a preceding stage is an inactive state of a subsequent logic stage, the logic function of the subsequent logic stage is in a non-conducting state when the output of the prior logic stage is in the precharge logic state. By providing the precharge to a subsequent stage-only after the output of the prior stage is in the precharge state, there can be no DC current flow during the precharge of the subsequent stage, and the need for an evaluation transistor to block the DC current flow during precharge is eliminated. The elimination of the evaluation transistor eliminates the delay introduced by the evaluation transistor in a precharge logic stage, reduces the circuit area for the logic stage, reduces the load on the clock circuit, and reduces the power consumption of each logic stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.