CMOS technology voltage booster
US6420926B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2000 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Dec 15, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CMOS technology voltage booster having plurality of charge-pump stages cascade connected together and driven by a plurality of phases, each stage having a terminating input node and a terminating output node, with at least one transistor connected therebetween that has its control terminal connected to an internal circuit node of the same stage and applied one of the phases. This voltage booster further includes a pair of additional circuit elements for transferring, onto the internal node, a potential exceeding the voltage at the input node by at least one threshold. A first of the additional elements is essentially a MOS transistor having its control terminal connected to the control terminal of that transistor that is connected between the input and the output of the stage, while the second additional element is an auxiliary capacitor having one end connected directly to the first additional element and connected to the internal node through a transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.