Variable offset amplifier circuit
US6420932B1 · kind B1 · utility
24Cited by
8References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2001 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Jun 29, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45371
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
First and second differential transistor pairs, where each is intentionally unbalanced, are provided. Each pair has first and second output nodes. The first output node of the first pair is coupled to the second output node of the second pair. The second output node of the first pair is coupled to the first output node of the second pair. First and second variable current generators are coupled to control respective tail currents of the first and second differential pairs. Applications of the amplifier circuit include sense amplifiers and comparators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.