High speed CMOS imager column CDS circuit
US6421085B1 · kind B1 · utility
23Cited by
32References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 14, 1998 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Apr 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/677
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A correlated double sampling unit within a CMOS imager employs an image sensor having a plurality of photodetectors arranged in a series of rows and columns with a row addressing circuit, a column addressing circuit, a first sample and hold circuit allocated for each of the columns, a transfer circuit operatively connecting each of the columns to the first sample and hold circuit for each of the columns, and a plurality of second sample and hold circuits, each of the second sample and hold circuits being operatively connected to a subset of the first sample and hold circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.