Solid electrolytic multilayer capacitor
US6421227B2 · kind B2 · utility
11Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2000 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Dec 11, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01G9/028
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A solid electrolytic capacitor is obtained by mounting a plurality of single plate capacitor elements within a chip by employing a stacking structure such as parallel stacking, opposing stacking, each layer-opposing stacking or closest stacking. As a result, a compact and high-capacitance element can be easily manufactured. The single plate capacitor element is preferably an element having an unfolded fan-like shape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.