Low-leakage MOS planar capacitors for use within DRAM storage cells
US6421269B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2000 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Oct 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/213
Abstract
A planar capacitor for use within a dynamic random access memory (DRAM) cell is operated within semiconductor depletion during normal storage operations to increase the charge retention time of the capacitor. Operation within semiconductor depletion allows a significant increase in charge retention time in a capacitor for which gate oxide leakage is the predominant leakage mechanism. The voltages that are applied to the storage cell during DRAM operation are controlled so that the storage capacitor within the cell remains in depletion during storage of both a logic zero and a logic one. Although the capacitance of the cell is decreased by operating in depletion, the charge retention time of the cell can be increased by multiple orders of magnitude. In one application, the inventive structures and techniques are implemented within a DRAM device that is embedded within logic circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.