Parallel computer with improved access to adjacent processor and memory elements
US6421772B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1999 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Jun 3, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel computer of this invention includes a plurality of memory elements and a plurality of processing elements and each of the processing elements is connected to logically adjacent memory elements. For example, the processing elements which corresponds to a logical position (i, j) is connected to the memory elements which correspond to a plurality of logical positions (i, j), (i, j+1), (i+1, j) and (i+1, j+1). It is preferable if each of the memory elements can be accessed from the exterior. According to this invention, efficient memory access can be made and the parallel processing can be performed at high speed without increasing the hardware amount and making the control operation complicated. Further, the operation speed of the image processing can be enhanced by constructing an image memory by use of a plurality of memory elements and causing the processing element to effect the image processing in a distributed and cooperative manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.