Programmable delay circuit having a fine delay element selectively receives input signal and output signal of coarse delay element
US6421784B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1999 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Mar 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00195
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable delay element having a fine delay circuit with fractional units of delay. The fine delay circuit has a fine delay circuit with a plurality of selectable delay paths, each delay path having an associated delay interval. The fine delay element is electrically-coupled to a data terminal for receiving and delaying an input signal. A control circuit is electrically-coupled to the fine delay circuit to select the delay path for the input signal. In a further aspect of the invention, the fine delay circuit is electrically-coupled to a coarse delay circuit having a plurality of selectable delay blocks in a repetitive block configuration. The coarse delay circuit is electrically-coupled to a second data terminal for receiving and inserting a second signal through said fine delay circuit. The control circuit is electrically-coupled to the selective delay path of the fine delay circuit and the coarse delay circuit such that either a fine delay, a coarse delay, or a coarse and a fine delay can be selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.