Method and apparatus for diagnosing memory using self-testing circuits
US6421794B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Mar 9, 2000 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Mar 9, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for diagnosing memory using self—testing circuits. A comparator compares actual data output from a RAM with expected output generated by built—in self—testing (BIST) circuitry. The comparator outputs a resulting initial fail vector which is subsequently input into a compressor. The compressor performs multiple logical operations on the initial fail vector to compress or reduce the bit—width of the initial fail vector, resulting in a compressed fail vector. Once generated, the compressed fail vector is fed to I/O terminals of the integrated circuit (IC) forming a stream of bits to be recorded by test equipment external to the IC. The recorded compressed fail vector is then utilized to reconstruct the initial fail vector that was generated by the bit comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.