Chipset-based memory testing for hot-pluggable memory
US6421798B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 1999 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Jul 14, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing memory of a system is disclosed which operates the system from a second area of system address space which is outside of a first area of system address space, the system having one or more physical memory devices associated with the first area of system address space. The memory locations associated with the first area of the system address space are tested for predetermined characteristics after which the one or more tested physical memory devices are replaced with respective untested physical memory devices without dropping power to the system, and tested by repeating the test cycle. The system is prevented from operating in the first area of system address space and forced to operate from the second area, thereby preventing system interruptions when replacing the physical memory devices for testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.