Testing IO timing in a delay locked system using separate transmit and receive loops
US6421801B1 · kind B1 · utility
64Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1999 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Jun 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/319
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for testing an input data path of an integrated circuit. Dual transmit and receive delay locked loops (DLLs) provide clocks for test mode data transmit and receive. Test mode logic drives a data pattern into an input receiver with the data pattern clocked by the transmit DLL and the input receiver clock by the receive DLL. The output of the input receiver is compared with the data pattern. The transmit DLL is adjusted relative to the receive DLL to measure setup and hold times of the data pattern driven through the input receiver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.