System and method for implementing hybrid automatic repeat request using parity check combining
US6421803B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 1999 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Oct 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/1874
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A telecommunications system and method for performing error detection on received data packets and error correction on only those data packets that were received in error without the need for retransmission of the data packets or parity checking bits. At the transmitter, the complete data packet is divided into a number of data units (DUs). The DUs are encoded for both error detection and error correction. Both the error correction and error detection parity check bits are separately combined into one or more blocks. Thereafter, the DUs and the block(s) containing the combined parity check bits are transmitted to the receiver. If the receiver determines that a received DU does not contain any errors, the error correction parity check bits for that DU are generated and their effect on the combined error correction parity check bits removed. Thereafter, the remaining error correction parity check bits, which now only contains information about the DUs actually in error, are used to correct the erroneous DUs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.