Hardware design language for the design of integrated circuits
US6421808B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1999 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Apr 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware design language V++ is described. V++ provides an automatically designed and implemented communications protocol, embedded by a compiler in the design itself. This protocol permits transparent, automatic communication between modules in a hardware design. The protocol generalizes current design practice and impacts neither the cycle time, nor the area, of a typical system. Incorporating this protocol in the language itself frees the designer from the task of writing communications code, and ensures that two communicating modules follow the same low-level protocol. In V++ each program is directly interpreted as a network of communicating finite state machines. The composition of two V++ programs is a V++ program, with well-defined, deterministic semantics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.