Method of manufacturing trench gate structure
US6423618B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1999 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Dec 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/608
Abstract
A method for manufacturing a trench gate structure of a power metal-oxide-semiconductor field-effect transistor. A substrate is provided, which substrate has a epitaxial layer thereon, a base region formed in the epitaxial layer, a source region formed in a portion of the base region, a first dielectric layer on the base region and the source region, a second dielectric layer on the first dielectric layer and a trench penetrating through the second and the first dielectric layers, the source region and the base region and into the epitaxial layer. A third dielectric layer is formed on the bottom of the trench. A conformal gate oxide layer is formed in the trench. A conformal polysilicon layer is formed on the second dielectric layer and in the trench. A fourth dielectric layer is formed on the polysilicon layer to fill the trench. Portions of the fourth dielectric layer and the polysilicon layer are removed until the surfaces of the fourth dielectric layer and the polysilicon layer are substantially level with the surface of the base region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.