NCO based frequency synthesizer with jitter modulation
US6424185B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 22, 1998 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | May 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/06
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An improved synchronization circuit has a numerically controlled oscillator (NCO) having an accumulator, a number line, and feedback line fed back from the accumulator output. The accumulator repeatedly adds the number represented on the number line and the number represented on the feedback line and feedbacks the result to the accumulator. The result rolls over to zero as would an odometer when it reaches a maximum value. When the number represented on number input is properly selected by, for example, a microprocessor, a data stream representing the most significant bit of the result has jitter. The synchronization circuit also has a phase-locked loop (PLL) configured to receive the data stream of the most significant bit. The frequency of the most significant bit stream and the frequency of the jitter on that bit stream are controlled by the number at the number input. The number is chosen to maximize the jitter frequency and thus maximize jitter attenuation through the PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.