Loop stabilization technique in a phase locked loop (PLL) with amplitude compensation
US6424230B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2000 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Sep 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/099
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop circuit and method that substantially decouples control of the phase/frequency and the amplitude of the oscillation output such that the frequency of the oscillation can be controlled independently of the amplitude. The phase locked loop circuit comprises a phase/frequency control loop and an amplitude control loop wherein both loops control an oscillator that oscillates at a certain frequency in response to a phase/frequency control signal generated by the phase/frequency control loop. In addition, the oscillation amplitude is determined by an amplitude control signal generated by the amplitude control loop. As with conventional circuits of this type, a parasitic gain is coupled from the amplitude control loop into the phase/frequency control loop, thereby causing interference between the loops that leads to stability problems. To counter the coupling of the parasitic gain, an inverted gain is inserted from the amplitude control loop into the phase/frequency control loop in opposite to the parasitic gain, so as to effectively cancel the interference. The circuit and method also provide for canceling the opposite parasitic gain that is coupled from the phase/fre…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.