Circuit for and method of driving a flat panel display in a sub field mode and a flat panel display with such a circuit
US6424325B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 3, 1998 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Nov 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/06
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A flat panel display (PD) comprises a plurality of display elements (C) arranged in a matrix of rows and columns, and electrodes (Sc, D, Su) associated to display elements (C) in a row or a column. The flat panel display (PD) is driven in a sub field mode wherein a field period (Tf) of a received display information (Pi) is divided (1) into consecutive sub field periods (Tsf) having an address period (Tp) preceding a display period (Ts). within a field period (Tf), a predetermined order of weight factors (Wf) each associated with a corresponding one of the display periods (Ts) is generated (1). The electrodes (Sc, D, Su) are interconnected in at least two groups (Sce, Sco; Sue, Suo). Drive signals corresponding to the weight factors (Wf) are supplied (2,3,4,5; 2,3,4,5,6) to each of the at least two groups. Within a same field period (Tf), the predetermined order of weight factors (Wf) is adapted to associate a different order of weight factors (Wf) to the display periods (Ts) of the at least two groups of electrodes (Sce, Sco; Sue, Suo).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.