Multidimensional addressing architecture for electronic devices
US6424553B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2001 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Mar 22, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/81
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device for providing addressability in an apparatus including one or more volume elements which together with the device form part of a matrix in the apparatus. The device establishes an electrical connection to specific cells by electrodes in the matrix and thereby defining a cell in the volume element. The device includes at least three sets of plural strip-like electrodes, the strip-like electrodes of each set being provided in substantially parallel relationship to each other in a two-dimensional and planar layer forming an additional part of the matrix. A set of strip-like electrodes in one layer is oriented at an angle to the projected angle of orientation of the electrode sets in proximal neighboring layers onto this one layer, such that the sets of strip-like electrodes in proximal neighboring layers exhibit a mutual non-orthogonal relationship.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.