System and method for increasing performance in a compilable read-only memory (ROM)
US6424556B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2000 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Jan 26, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compilable ROM architecture with enhanced performance characteristics, i.e., increased speed and lowered power consumption, wherein a plurality of memory locations are organized into one or more I/O blocks, each having a select number of bitlines. At least a portion of the data map in the ROM is manipulated so as to achieve a desired distribution of 0's and 1's such that the loading of 0's on the bitlines is reduced. In one exemplary embodiment, the data map is inverted per bitline, per I/O, or both. Output path circuitry is appropriately manipulated for accurate outputting of the original data. In another embodiment, the data is stored in the ROM using a scrambled addressing scheme wherein a portion of the row and column addresses is interchanged in order to minimize bitline loading of the binary 0's.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.