System and measuring access time of embedded memories
US6424583B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2000 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Nov 30, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A BIST controller and a separate measurement circuit are used to determine the maximum time period for accessing data stored in an embedded integrated circuit memory. The BIST controller includes a finite state controller for controlling the state of said BIST, a pattern generator for generating a patterned stimulus to be applied to the memory, and a comparator for comparing the response of said memory to said stimulus, to a reference response. The measurement circuit includes a pair of logic circuits for respectively operating on “1's” and “0's” data read from the memory, and a plurality of time delay elements that introduce time delays in the data prior to delivery to the logic circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.