Semiconductor integrated circuit having circuit for correcting data output timing
US6424592B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 2000 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Nov 30, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit includes a DLL circuit generating an internal clock signal, a plurality of clock generators generating respective output clock signals based on the internal clock signal, a plurality of output buffers outputting to a plurality of data input/output pins data according to corresponding output clock signals respectively, and a selection circuit. The selection circuit outputs a code signal for allowing the timing of the earliest output clock signal to conform to the timing of the latest output clock signal. A predetermined clock generator adjusts the timing of the output clock signal according to the code signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.