Multi-layer switching apparatus and method
US6424659B2 · kind B2 · utility
216Cited by
14References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 17, 1998 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Jul 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/351
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Multilayer switching device and associated technique enables simultaneous wire-speed routing at OSI layer 3, wire-speed switching at layer 2, and support multiple interfaces at layer 1. Implementation may be embodied using one or more integrated circuits (ASIC), RISC processor, and software, thereby providing wire-speed performance on interfaces, in various operational modes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.