BPSK encoder circuit
US6424682B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 1999 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | May 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2035
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A BPSK encoder is provided with a first circuit which processes a carrier signal and a binary signal to be encoded, and produces an output binary signal having synchronous phase shifts representing a change in the value of the signal to be encoded. Also, the first circuit is provided with a sampling signal from a second circuit. The second circuit includes a delay circuit to deliver a shifted carrier signal that is smaller than the half-period of the carrier signal, and a logic gate for the logic combination of the carrier signal and the shifted carrier signal. The logic gate also delivers a binary sampling signal having at least two leading or trailing edges at each period of the carrier signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.