Parallel processor
US6424870B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1998 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Aug 7, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99944
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A parallel processor system has a plurality of nodes interconnected by a network for communication under control of a network interface controller of each node. The network interface controller includes a message reception controller for receiving a message from another node and judging illustratively the status of message reception and the need to return an acknowledge message; an acknowledge generating unit for generating an acknowledge message transmission request based on predetermined information in the message and the reception status when the return of an acknowledge message is judged to be necessary; and a message transmission controller for receiving an acknowledge the message transmission request and generating and returning an acknowledge message correspondingly. At the receiving node, the network interface controller can return an acknowledge message without processor intervention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.