Systems and methods for passively transferring data across a selected single bus line independent of a control circuitry
US6425020B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 18, 1997 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Apr 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processing circuiter 100 is provided having a passive data transfer capability. Processing circuitry 100 includes a bus 116, a first subsystem 105 coupled to bus 116 through first passive transfer logic 120a, and a second subsystem 108 coupled to bus 116 through second passive transfer logic 120b. Processing circuitry 100 further includes control circuitry 101/103 coupled to bus 116 for initiating a passive data transfer between first and second subsystems 105 and 108, first and second passive transfer logic 120a and 120b there after controlling exchange of data between the first and second subsystems 105 and 108 independent of the control circuitry 101/103.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.