Load balancing configuration for storage arrays employing mirroring and striping
US6425052B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 28, 1999 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Oct 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array of storage devices may be provided in which data is both striped and mirrored across the array. Data may be organized in stripes in which each stripe is divided into a plurality of stripe units. The stripe units may be mapped sequentially to consecutive storage devices in the array for each data stripe. Each data stripe is also mirrored within the array as a mirrored data stripe. Each mirrored data stripe is also divided into a plurality of stripe units. The stripe units of the mirrored stripes are distributed throughout the array according to a mapping that provides for load balancing during a reconstruction operation. According to one embodiment, stripe units for mirrored stripes are distributed according to a rotational group such that each mirrored stripe is rotated on the array by one more position than the previous mirrored stripe and wherein the rotational group is repeated as necessary. Alternatively, the mirrored stripe units may be distributed according to other permutations to improve load balancing during reconstruction of a failed device. In other embodiments, in addition to mapping mirrored stripe units to balance read operations during reconstruction, one or…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.