Variable length instruction decoder
US6425070B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1998 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | Mar 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7857
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. Furthermore, additional aspects of the invention are realized by having instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. Thus, multiple operations are performed during each clock cycle, reducing the total number of clock cycles necessary to perform a task. The exemplary DSP includes a set of three data buses over which data may be exchanged with a register bank and three data memories. The use of more than two data buses, and especially three data buses, realizes another aspect of the invention, which is significantly reduced bus contention. One embodiment of the invention calls for the data buses to include one wide bus and two narrow buses. The wide bus is coupled…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.