Method and apparatus for testing an impedance-controlled input/output (I/O) buffer in a highly efficient manner
US6425097B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 1999 |
| Grant date | Jul 23, 2002 |
| Priority date | — |
| Expiry date | May 27, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3004
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for efficiently testing input/output (I/O) buffer are disclosed. The I/O buffer includes multiple transistors coupled to a data output terminal. The method includes enabling a single one of the multiple transistors. A predetermined electrical voltage level is then forced upon the data output terminal, and a resultant electrical current flowing through the data output terminal (e.g., in a direction away from the I/O buffer) is measured. The measured electrical current is compared to predetermined minimum and maximum current values. A ratio of the measured electrical current to a reference current is computed, and the computed current ratio is compared to a predetermined minimum and maximum current ratio. The above steps may be repeated until each of the multiple transistors has been enabled. The drive strength of a given transistor is a measure of the amount of electrical current the transistor causes to flow through the data output terminal when enabled. One or more of the multiple transistors has a drive strength which is less than all of the other transistors (i.e., a minimum drive strength). The reference current may be the amount of electrical current flo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.