Shift register
US6426743B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2000 |
| Grant date | Jul 30, 2002 |
| Priority date | — |
| Expiry date | Feb 9, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G3/3677
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a shift register for driving a pixel row in a liquid crystal display device a plurality of stages are connected: to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator; to row lines; and in cascade, with respect to a scanning signal, for charging and discharging the row lines. Each stage of the shift register has a pull-up transistor, a pull-down transistor, and first to fourth transistors. The pull-up transistor has a control electrode and a conduction path connected between the first clock signal line and the output terminal. The pull-down transistor has a control electrode and a conduction path connected between the low level voltage line and the output terminal. The first and second transistors have conduction paths connected in series between the input terminal and the control electrode of the pull-up transistor, and each has a control electrode connected commonly to the second clock signal line. The first and second transistors allow a voltage to be charged on the control electrode of the pull-up transistor. The third and fourth transistors have conduction paths connected in series between the third clock signal line and the c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.