Shared ground SRAM cell
US6426890B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2001 |
| Grant date | Jul 30, 2002 |
| Priority date | — |
| Expiry date | Jan 26, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell layout provides for sharing of power supply connections between adjacent rows and columns of a memory array, respectively by providing a subarray layout in which one power connection is serpentine, extending into adjacent rows, and another stitches together a connection of memory cells in adjacent columns and adjacent rows. The subarray layout may be expanded by reflection and produced by lithographic exposures of relatively large numbers of memory cells in a step-and-repeat fashion. The layout of the power connections to the memory cells allows a significant reduction in the number of power connections required and/or the provision of redundant connections and a shielding mesh without increase of the number of connections required as well as full exploitation of minimum feature size with increased manufacturing yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.