Synchronous semiconductor memory device performing data output in synchronization with external clock
US6426900B1 · kind B1 · utility
39Cited by
1References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2001 |
| Grant date | Jul 30, 2002 |
| Priority date | — |
| Expiry date | Jul 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A DLL circuit generates a control clock specifying an operating timing of a data output buffer according to an external clock. The DLL circuit includes a replica delay time adjusting section and a phase control section. The phase control section controls such that a feedback clock and the external clock becomes in phase. The replica delay time adjusting section adjusts a delay time of the feedback clock behind the control clock according to an operating condition serving as a factor for changing a processing time of the data output buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.