Separate code and data contexts: an architectural approach to virtual text sharing
US6427162B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 2, 1996 |
| Grant date | Jul 30, 2002 |
| Priority date | — |
| Expiry date | May 2, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a processor including a core unit for processing requests from at least one process. The at least one process has a code portion with at least one segment having a first code context identifier. The at least one process also has a data portion with a first data context identifier. The processor further includes a first storage device for storing code address translations and a second storage device for storing data address translations. The processor also includes a code context register coupled to the core unit and to the first storage device, for storing a second code context register. The processor also includes a data context register, coupled to the core unit and to the second storage device for storing a second data context identifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.